In recent years, with the increasing speed of CPUs and so forth, semiconductor integrated circuit apparatuses that use low-voltage drive have been developed, and it has become common for terminals of a plurality of power supplies whose signal levels differ to be connected to the same bus, and for multi-potential interface signals to be generated. In this case, an output circuit is used that has a tolerant configuration in which a current does not flow in reverse in a power supply voltage from an output terminal.
In Patent Document 1 (Unexamined Japanese Patent Publication No. HEI 5-284001), an output circuit is disclosed that, when a power supply of one integrated circuit among a plurality of integrated circuits is turned off, prevents reverse inflow from an output terminal to another integrated circuit.
FIG. 1 is a circuit diagram of an output circuit described in Patent Document 1.
As shown in FIG. 1, output circuit 10 is configured by means of an output buffer comprising P-channel MOS (Metal Oxide Semiconductor) transistor Q21 whose source is connected to low-voltage power supply VDD14 and N-channel MOS transistor Q22 whose source is connected to ground terminal 3, and N-channel MOS transistor Q23 whose source and drain are connected between a connecting point of MOS transistors Q21 and Q22 and output terminal 13, and whose gate is connected to high-voltage power supply 15. Also, output circuit 10 is provided with an input protection circuit that uses input terminals 11 and 12, output terminal 13, logic elements 24, 25, and 26, and parasitic diodes D21 and D22.
The gates of P-channel MOS transistor Q21 and N-channel MOS transistor Q22 of output circuit 10 are configured so as to control signals input from input terminals 11 and 12 via logic elements 24, 25, and 26. In the above configuration, low-voltage power supply VDD14 is supplied from high-voltage power supply via a regulator, and is turned on/off in conjunction with high-voltage power supply 15.
In the above configuration, in normal operation, low-voltage power supply VDD14 and high-voltage power supply 15 are applied to output circuit 10, and N-channel MOS transistor Q23 is in an on state. Operation is performed whereby a control signal is output to output terminal 13 by means of control of signals from input terminals 11 and 12. On the other hand, when high-voltage power supply 15 is in an off state, low-voltage power supply VDD14 becomes 0 V, but since N-channel MOS transistor Q23 is turned off, reverse inflow of current from output terminal 13 is prevented.
In Patent Document 2 (Unexamined Japanese Patent Publication No. 2008-131305), a semiconductor switch circuit is disclosed that enables current consumption to be reduced in a conducted state.
FIG. 2 is a circuit diagram of a semiconductor switch circuit described in Patent Document 2.
As shown in FIG. 2, semiconductor switch circuit 30 has a configuration provided with P-channel MOS transistors Q41 and Q42 for conduction that are connected in series and that share a source between input/output terminal 31 and input/output terminal 32, P-channel MOS transistor Q43 and N-channel MOS transistor Q45 whose drains are connected to the gate of Q41, P-channel MOS transistor Q44 and N-channel MOS transistor Q46 whose drains are connected to the gate of Q42, and control terminal 33 connected to the gate of each transistor, in which the sources and back-gates of Q43 and Q44 are connected to the sources of Q41 and Q42, and switching between conducted/non-conducted between input/output terminal 31 and input/output terminal 32 is performed by voltage control by means of voltage value Vcont of a control signal applied to control terminal 33.
In the above configuration, semiconductor switch circuit 30 switches P-channel MOS transistors Q41 and Q42 between conducted/non-conducted by control terminal 33 control of the voltage applied to input/output terminal 31 or input/output terminal 32. By this means it is possible for semiconductor switch circuit 30 to operate as a semiconductor switch circuit. Thus, even if a control signal is not applied to control terminal 33, reverse inflow is prevented between input/output terminals 31 and 32, and a non-conducted state is implemented dependably.
However, the following kinds of problems are associated with such conventional semiconductor integrated circuits.
With the output circuit described in Patent Document 1, since output circuit low-voltage power supply VDD14, and high-voltage power supply 15 having higher potential than low-voltage power supply VDD14 for performing on/off control of N-channel MOS transistor Q23, are necessary, a dual-power-supply configuration with two different potentials is necessary.
Also, with combinations of input terminal 11 high and input terminal 12 low, and input terminal 11 low and input terminal high, P-channel MOS transistor Q21 and N-channel MOS transistor Q22 are turned off at the same time. When N-channel MOS transistor Q23 is on, there is a potential resulting from adding together the potentials of P-channel MOS transistor Q21 parasitic diode D21 and VDD14 at output terminal 13, and when this potential or higher is attained, reverse inflow of current to low-voltage power supply VDD14 occurs via parasitic diode D21.
Thus, high-voltage power supply 15 that controls N-channel MOS transistor Q23 is defined as the high potential of the output circuit. However, when output terminal 13 is at a high level when the impedance of an element connected to output terminal 13 is low, the potential between the gate and source of N-channel MOS transistor Q23 becomes large, the potential that should be supplied falls below the potential of low-voltage power supply VDD14, and an adequate dynamic range may not be able to be secured.
The semiconductor switch circuit described in Patent Document 2 is an excellent semiconductor switch circuit that enables a non-conducted state to be maintained dependably between switch terminals even if a control signal has ceased to be applied to a control terminal, and that can be implemented with an extremely simple circuit configuration. However, semiconductor switch circuit 30 described in Patent Document 2 is a circuit for which operation as a semiconductor switch circuit is assumed, and is not optimized as an output circuit. That is to say, in the case of semiconductor switch circuit 30, operation as a semiconductor switch circuit is assumed whereby P-channel MOS transistors Q41 and Q42 simultaneously go to the off state or simultaneously go to the on state since gates of P-channel MOS transistors Q43 and Q44 and N-channel MOS transistors Q45 and Q46 are common. Open-drain operation or push-pull operation necessary for an output circuit is not envisaged for semiconductor switch circuit 30.